1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a semiconductor device which includes a bipolar transistor, is capable of suppressing the Kirk effect and is also capable of a high-speed operation, and a method of manufacturing the same.
2. Description of the Prior Art
In order to obtain a high-speed switching performance in a bipolar transistor, the maximum oscillating frequency (to be abbreviated as fmax hereinafter) as one of performance indices must be increased. This fmax is given by the following equation: EQU fmax=(fT/8.pi..multidot.Rb.multidot.C.sub.BC).sup.1/2
where fT is the cut-off frequency, Rb is the base resistance, and C.sub.BC is the base-collector capacitance. It is apparent from the above equation that, in order to increase fmax, the cut-off frequency fT must be increased, the base-collector capacitance C.sub.BC must be decreased, and the base resistance Rb must be decreased. In recent years, in order to improve fmax to thereby improve the performance of the bipolar transistor, it has become more and more important to further increase the cut-off frequency and to decrease the base-collector junction capacitance or at least to minimize any increases in this capacitance.
Conventionally, in order to increase the cut-off frequency fT, scaling in the vertical direction, in particular in the direction of thickness of the base layer, has been performed. In order to decrease the base-collector capacitance and the base resistance, scaling in the planar direction has been performed by using a self alignment type bipolar transistor structure as shown in FIG. 1. Referring to FIG. 1, for example, reference numeral 111 denotes a p-type silicon substrate; 112, an n-type buried collector layer; 113, an n-type epitaxial layer; 114, 119, and 120, insulating films, e.g., silicon oxide films; 116, a base contact polycrystalline silicon layer; 117, a p-type external base diffusion layer; 118, a p-type intrinsic base; 115, a collector contact diffusion layer; 121, an emitter polycrystalline silicon layer; and 122, an n-type emitter diffusion layer, respectively.
As is generally known well, during a high-current injection operation the effective base width of a bipolar transistor increases in accordance with an increase in injection current. This is the so-called Kirk effect which is a major factor that degrades the high-speed operating performance. It is, therefore, important to decrease this Kirk effect. Conventionally, many methods of forming a pedestal collector region have been proposed in order to suppress the Kirk effect. For example, as shown in FIG. 2A, an n-type impurity is ion-implanted at a high concentration through an emitter-base forming opening portion 200 formed between a base contact electrode 216 and an insulating film 219, thus forming a pedestal collector region 201.
However, with this technique for suppressing the Kirk effect by forming a region doped with an impurity at a relatively high concentration immediately under the base-collector junction, since the base-collector junction capacitance increases, the transistor operation speed in the low-current injection decreases inversely. Also, the resistance of a region extending from the internal base to the external base, i.e., a so-called link base region, increases. These problems largely degrade the high-frequency characteristics of the transistor, as described above.
In order to solve these problems, as shown in FIG. 2B, there has been proposed a technique for forming a side wall 220 made of an insulating film on the side wall of an opening portion 200, and ion-implanting an n-type impurity at a high concentration through the opening portion 200, so that an n-type pedestal collector region 201 is selectively formed under an intrinsic base 218 immediately beneath the emitter region. As shown in FIG. 2C, Japanese Unexamined Patent Publication No. 5-259175 proposes a technique for forming a conductive layer 221 forming part of the emitter electrode in the emitter forming opening portion, and ion-implanting an n-type impurity at a high concentration to form a pedestal collector region 201. In this technique, the area of the pedestal collector region can be further decreased by self alignment, so that the base-collector parasitic capacitance can be decreased.
However, in each of the semiconductor devices shown in FIGS. 2B and 2C, although the base-collector parasitic capacitance can be decreased, the Kirk effect cannot be suppressed completely. This is due to the following reason. When the collector current increases, this collector current causes a so-called emitter clouding phenomenon (refer to reference symbol E in FIG. 2D) and mainly flows around the emitter diffusion layer. This emitter clouding phenomenon is described in, e.g., OHTA Kuni-icnhi, "Introduction to VLSI", Ohm Sha, pp. 30 to 31. If the pedestal collector region is formed immediately under an emitter diffusion layer 222 or on only a region narrower than the emitter diffusion layer 222, as described above, the Kirk effect occurs at the end portion of the emitter diffusion layer 222, as shown in FIG. 2D. Then, when a high-current injection operation is started, the cut-off frequency immediately decreases despite the presence of the pedestal collector region 201.